Non-public Island Lab Train One: I2C Slave Evaluation with FPGA  Debugger

Non-public Island Lab Train One: I2C Slave Evaluation with FPGA Debugger


That is the primary (draft) lab in a sequence of lab experiments /
workouts to assist the developer turn into acquainted with the FPGA
structure & instruments for Non-public Island. It assumed that the developer has
already constructed pictures for each the FPGA and Okay02 ARM micro controller
(µC). Additionally, the developer must be conversant in the opposite
associated documentation on this web site (see beneath).

This explicit lab walks the developer by means of establishing the Reveal
debug information and session to allow them to view the inner workings of the
I2C slave circuit. The µC sends instructions to the inner FPGA
controller (controller.v) by way of the I2C bus. The command set is
outlined within the article Non-public Island Exterior Register and Reminiscence
. Instance instructions embody reseting the PHYs, peeking and
poking PHY registers, and polling the Ethernet line standing.

Observe that this text was created utilizing Git commit bbe7e48e. A developer has the choice to both
re-create the Reveal information which are proven beneath or open the labs.rvl
and labs.rva information included within the Diamond mission underneath the
boards folder.

When you’re working with an oscilloscope, there’s additionally an choice to
mirror the I2C bus on the Arduino-compatible COMMUNICATION connector
pins: SCL and SDA. See the Darsena Specification for pin particulars.
You will additionally wish to be sure DEBUG_I2C is outlined underneath Debug
Choices in definitions.v

Some notes concerning the present I2C implementation:

  • The code wants a clear up and this will probably be executed summer season 2019.
  • The “devoted reminiscence interface” referred to within the code is
    not supported and could also be eliminated. SPI is at present used to interface
    with the FPGA inside recollections.
  • SCL (I2C clock) is routed as a knowledge sign and is sampled by
    the inner 10 MHz clock (clk_10). When you’re conversant in
    I2C, that SCL actually is not a clock and knowledge (SDA) is outlined
    as secure when SCL is excessive. Sampling SCL by a sooner clock permits for
    deglitching the road and eliminates the necessity to use a main clock
    lane for SCL.

Reveal Inserter

The determine beneath exhibits the Lattice Reveal Inserter for lab_1_i2c.
We add indicators to be traced by dragging them into the Hint Window from
the Design Tree. When you’re unfamiliar with Reveal, please evaluation the
Reveal Consumer Information. It is a fast learn and is effectively written.

Not proven is the Set off Sign Setup pane. We merely add the begin
sign as our TU (Set off Unit). Additionally be aware that we’re utilizing the highest
degree clk_10 clock as our pattern clock.

Determine 1. Reveal Inserter for Lab One: I2C

Reveal Analyzer

The 2 traces beneath have been generated in a dwell system whereas stepping
by means of the µC ecp5_pcs_init() routine in ecp5_driver.c.

Determine 2 is generated when stepping over:

i2c_write(pXfer,I2C_ECP5_ADDR, (uint8_t*) &pcs_s, sizeof(pcs_s));

When you search for cont_we pulsing excessive, you may see that the information
being clocked is 0x70, 0xd, which is ASCII “P CR”

Determine 2. I2C Write

Determine three is generated when stepping over:

i2c_read(pXfer, I2C_ECP5_ADDR, (uint8_t*) pBuff, eight);

When you search for fifo_re pulsing excessive, you may see that the information
being learn is 0x30, 0x30, 0x33, 0x30, which is ASCII “zero030”, and this
is the present worth of the inner PCS standing register.

Determine three. I2C Learn

We’ll hold including to this I2C lab and in addition create new ones because the yr
progresses. When you’re a scholar and serious about engaged on this
mission, please go to our Schooling hyperlink on the prime of this web page.

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