Supercon Keynote: Dr. Megan Wachs on RISC-V

Supercon Keynote: Dr. Megan Wachs on RISC-V

Hackaday has open-source working deep in our veins — and that goes for hardware in addition to software program. In any case, it’s nice to run open-source software program, but when it’s working on black-box hardware, the system is barely half open. Whereas software program has benefited mightily from the entire benefits of neighborhood improvement, the hardware world has been solely lately catching up. And so we’ve been following the RISC-V open-source CPU improvement with our full consideration.

Dr. Wachs, making her personal wedding ceremony ring.

Our keynote speaker for the 2019 Hackaday Superconference is Dr. Megan Wachs, the VP of Engineering at SiFive, the corporate based by the creators of the RISC-V instruction-set structure (ISA). She has additionally chaired the RISC-V Basis Debug Activity Group, so it’s secure to say that she is aware of RISC-V in and out. If there’s one discuss we’d like to listen to on the previous, current, and way forward for the structure, that is it.

The RISC-V isn’t a specific chip, however somewhat it’s a design for the way a CPU works, and a typical for the lowest-level language that the machine speaks. In distinction to proprietary CPUs, RISC-V CPUs from disparate distributors can all use the identical software program instruments, unifying and opening their improvement. Furthermore, open hardware implementations for the silicon itself imply that new gamers can enter the house extra simply, deliver their distinctive concepts to life sooner, and we’ll all profit. We will all work collectively.

It’s no coincidence that this 12 months’s Supercon badge has two RISC-V cores working in its FPGA cloth. Once we went purchasing round for an open CPU core design, we had just a few full RISC-V techniques to select from, full compiler and improvement toolchains to jot down code for them, and naturally, implementations in Verilog able to flash into the FPGA. The wealthy, open ecosystem round RISC-V made it a no brainer for us, simply because it does for firms making neural-network peripherals and even commodity microcontrollers. You’ll be seeing much more RISC-V techniques within the close to future, in your workbench and in your pocket.

We’re tremendously excited to listen to extra in regards to the undertaking from the within, and completely wanting ahead to Megan’s keynote speech!

The Hackaday Superconference is totally offered out, however that doesn’t imply that you need to miss out. We’ll be live-streaming the keynote and all different talks on the Supercon major stage, so subscribe our YouTube channel and also you gained’t miss a factor.

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